In semiconductor integrated circuits, with the improvement of fine fabrication process, reduction of an operating voltage has been made. However, LSIs including a plurality of power supply voltages have been increased so as to enable a circuit which cannot be operated at a low-voltage to operate. The frequency of a circuit operation (such as 500 MHz or higher) has been made higher in order to realize wireless high-speed communication.
It is necessary for a level shift circuit of a semiconductor integrated circuit to pass a high-frequency signal from a low-voltage power supply to a high-voltage power supply while maintaining the duty ratio of an input signal. Generally, the variation in the duty ratio of an output signal with respect to the input signal in the level shift circuit is caused by a difference in an inclination (slew rate) in a rise/fall of each of the input and output signals. When the signal has a high frequency (500 MHz or more), the duty ratio is significantly affected even by a slight variation of inclination in the rise/fall of the signal. Accordingly, the development of a level shift circuit that is able to maintain duty ratio at a high frequency (500 MHz or more) has been desired.
FIG. 5 (which is FIG. 1 in Patent Document 1) is a diagram showing a configuration of a level shift circuit disclosed in Patent Document 1. As shown in FIG. 5, a level shift circuit 100 receives at an input terminal IP thereof an output of an inverter NOT1 corresponding to a voltage amplitude between a first power supply voltage Vdd1 and a ground voltage GND and converts the level of the received signal to a signal of a voltage amplitude between a second power supply voltage Vdd2 and the ground voltage GND. A resistor element R1 for pull-up is connected between a second power supply terminal T2 and an output terminal OUT, and an N-channel MOS transistor Q1 is connected between the output terminal OUT and a ground terminal TG. A P-channel MOS transistor Q2 is connected in parallel with the resistor element R1 between the second power supply terminal T2 and the output terminal OUT. A gate electrode of the N-channel MOS transistor Q1 is connected to the input terminal IP. There are also provided a resistor element R2 and a capacitor C1 connected in series from the second power supply terminal T2 in the stated order. A gate electrode of the P-channel MOS transistor Q2 is connected to a connection node of the resistor element R2 and the capacitor C1. An input terminal of an inverter NOT1 is connected to an input terminal IN, and the inverter NOT1 inverts an input signal (a signal equivalent to the voltage amplitude between the first power supply voltage Vdd1 and the ground voltage GND) supplied from the input terminal IN to output the inverted signal.
FIGS. 6A to 6F are timing charts showing an operation of the circuit in FIG. 5 (based on FIG. 2 in Patent Document 1). An operation of the level shift circuit 100 will be described with reference to FIGS. 5 and 6.
FIG. 6A is a timing chart of an input signal IN to the inverter NOT1 in FIG. 5;
FIG. 6B is a timing chart of an output signal of the inverter NOT1 in FIG. 5;
FIG. 6C is a timing chart of turning on (ON)/off (OFF) of the N-channel MOS transistor Q1 in FIG. 5;
FIG. 6D is a timing chart of a voltage at the gate electrode (terminal voltage of the capacitor C1) of the P-channel MOS transistor Q2 in FIG. 5;
FIG. 6E is a timing chart of turning on (ON)/off (OFF) of the P-channel MOS transistor Q2 in FIG. 5; and
FIG. 6F is a timing chart of an output signal of the level shift circuit 100 in FIG. 5. FIG. 6D shows a threshold voltage Vth of the P-channel MOS transistor Q2 as well.
<Rise Operation of Output Signal>
A rise operation of the output signal of the level shift circuit 100 will be described. Assume that the input signal to the inverter NOT1 changes from Low to High (from the ground voltage GND to the first power supply voltage Vdd1) (as shown in FIG. 6A), and then the output signal of the inverter NOT1 changes from High to Low (from the first power supply voltage Vdd1 to the ground voltage GND) (as shown in FIG. 6B). At this timing of the change, the N-channel MOS transistor Q1 changes from ON to OFF (as shown in FIG. 6C). In this case, electric charges are charged at the capacitor C1, and a potential difference of (Vdd2-Vdd1) is produced between two electrodes of the capacitor C1. For this reason, at a moment when a voltage at a low-potential side electrode (electrode on the side connected to the output of the inverter NOT1) of the capacitor C1 varies from the first power supply voltage Vdd1 to the ground voltage GND, the gate voltage of the P-channel MOS transistor Q2, or a voltage at a high-potential side electrode (electrode connected to the resistor element R2) of the capacitor C1 varies from the second power supply voltage Vdd2 to (Vdd2-Vdd1) (as shown in FIG. 6D). With this variation, when the voltage at the high-potential side electrode (electrode connected to the resistor element R2) of the capacitor C1 reaches (falls to) the threshold voltage Vth, the P-channel MOS transistor Q2 changes from OFF to ON (as shown in FIG. 6E). A voltage at the output terminal OUT of the level shift circuit 100 instantaneously changes from Low to High (from the ground voltage GND to the second power supply voltage Vdd2).
Then, according to a time constant defined by a resistance value of the resistor element R2 and a capacitance of the capacitor C1, electric charges are charged into the capacitor C1 from the second power supply terminal T2 through the resistor element R2 with an elapse of time. Then, when the voltage at the high-potential side electrode of the capacitor C1 (electrode on the side connected to the resistor element R2) becomes higher than the threshold voltage Vth (as shown in FIG. 6D), the P-channel MOS transistor Q2 turns OFF (as shown in FIG. 6E). When the P-channel MOS transistor Q2 turns on, the gate voltage of the P-channel MOS transistor Q2 or the voltage at the high-potential side electrode of the capacitor C1 instantaneously falls to (Vdd2-Vdd1). It is because the inverter NOT1 is configured so that an output impedance of the inverter NOT1 becomes negligibly smaller than an impedance of the resistor element R1. A discharge time constant of the capacitor C1 is negligibly reduced, so that the capacitor C1 instantaneously discharges.
<Fall Operation of Output Signal>
Next, a fall operation of the output signal of the level shift circuit 100 will be described. Assume that the input signal to the inverter NOT1 changes from High to Low (from the first power supply voltage Vdd1 to the ground voltage GND) (as shown in FIG. 6A), and then the output signal of the inverter NOT1 changes from Low to High (from the ground voltage GND to the first power supply voltage Vdd1) (as shown in FIG. 6B). At this timing of the change, the N-channel MOS transistor Q1 changes from OFF to ON (as shown in FIG. 6C). In this case, electric charges are charged at the capacitor C1, and a potential difference of (Vdd2-GND) is produced between the two electrodes of the capacitor C1. When the voltage at the low-potential side electrode (electrode on the side connected to the output of the inverter NOT1) varies from the ground voltage GND to the first power supply voltage Vdd1, the gate voltage of the P-channel MOS transistor Q2, or the voltage at the high-potential side electrode (electrode connected to the resistor element R2) of the capacitor C1 instantaneously increases from the second power supply voltage Vdd2 to (Vdd2+Vdd1) (as shown in FIG. 6D).
Even if the gate voltage of the P-channel MOS transistor Q2 increases, the P-channel MOS transistor Q2 does not turn on (as shown in FIG. 6E). According to the time constant defined by the resistance value of the resistor element R1 and the capacitance of the capacitor C1, the voltage at the high-potential side electrode of the capacitor C1 falls with an elapse of time, and is stabilized at the second power supply voltage Vdd2. Further, the N-channel MOS transistor Q1 turns on. The voltage at the output terminal OUT changes from High to Low (from the second power supply voltage Vdd2 to the ground voltage GND).
[Patent Document 1]
    JP Patent Kokai Publication No. JP2006-352502A (FIGS. 1 and 2)